1. Field of the Invention
Embodiments of this invention relate generally to computers, and, more particularly, to a method, system and apparatus for a low-voltage, maskable graphics processing memory.
2. Description of Related Art
General purpose computing systems, such as personal computers, have evolved from relatively simple display tasks to complex tasks that involve high resolution images and multimedia offerings. Systems that require complex, processor intensive graphics capabilities also have higher voltage requirements, and thus higher power requirements. As computer systems become more complex and user applications increase in system resource usage, there is an increased need for memory that consumes less power for graphics processing.
Typically, modern memory implementations for graphics processing have involved cell configurations, such as 6T and 8T cells. Such memories often consist of an array of “cells,” also called “bitcells,” each comprised of metal oxide semiconductor field effect transistors (MOSFETs). Memories constructed from these cells and bitcells have several drawbacks. For example, masking a cell to avoid writing data to the cell is a common task in graphics memories; however, it, is complex and voltage/power intensive in 6T and 8T cells. Lines used to write data in current 6T and 8T write-maskable cells must be pre-charged at the beginning of each data cycle, and then driven again later in the cycle. Driving lines twice per cycle is costly in terms of power consumption and line control complexity. Additionally, the pre-charging phase is time consuming and requires the memory to operate at a slower overall frequency.
Previous configurations of 10T cells also have drawbacks that make them unsuitable for use in graphics memory. For example, previous 10T cells, as well as 6T and 8T cells, utilize a single write enable line, and thus a single pair of pass transistors. If bit masking is desired in the case of a single pass transistor pair implementation, the pass transistors needs to be sized for both read and write operations. However, pass transistors are typically sized small for read operations and sized large for write operations. Because only a single pair of pass transistors is used, the transistors' size cannot be optimized for both read and write operations, nor can the size be optimized for either a read or a write operation because both operations must be performed. Thus, the optimal size must be compromised. In other words, the single pass transistor pair model cannot be sized to the optimal area for a read (smaller) or sized to the optimal area for writes (larger); rather the single pair pass transistor model must have transistors sized in between the optimal read and write sizes. This non-optimization decreases voltage/power efficiency.
Previous configurations of 10T cells that do not require a pre-charge operation suffer from other drawbacks as well. In particular, these types of 10T cells lack the ability to mask bits during write operations. Other existing 10T cells may provide for the ability to mask bits, but at a cost of increased voltage. Such 10T cell configurations require write bitlines that are differential, which leads to sizing issues with pass transistors (MOSFETs) similar to the issues seen with single write enable (i.e., single pass transistor) configurations. In other words, the pass transistors coupled to the differential write bitlines cannot be sized to the optimum area for both reads and writes. The transistors must be sized down to accommodate read stability in addition to being large enough to allow writeability. This non-optimization decreases voltage/power efficiency because the memory cell is less writeable at lower voltages. Any decrease in operating voltage in these 10T cells is gained at the cost of a slower operational frequency.